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Showing 1 - 5 of 5 matches in All Departments
Efficient design of embedded processors plays a critical role in
embedded systems design. Processor description languages and their
associated specification, exploration and rapid prototyping
methodologies are used to find the best possible design for a given
set of applications under various design constraints, such as area,
power and performance.
Over the past decade, system-on-chip (SoC) designs have evolved to
address the ever increasing complexity of applications, fueled by
the era of digital convergence. Improvements in process technology
have effectively shrunk board-level components so they can be
integrated on a single chip. New on-chip communication
architectures have been designed to support all inter-component
communication in a SoC design. These communication architecture
fabrics have a critical impact on the power consumption,
performance, cost and design cycle time of modern SoC designs. As
application complexity strains the communication backbone of SoC
designs, academic and industrial R&D efforts and dollars are
increasingly focused on communication architecture design.
This Open Access book introduces readers to many new techniques for enhancing and optimizing reliability in embedded systems, which have emerged particularly within the last five years. This book introduces the most prominent reliability concerns from today's points of view and roughly recapitulates the progress in the community so far. Unlike other books that focus on a single abstraction level such circuit level or system level alone, the focus of this book is to deal with the different reliability challenges across different levels starting from the physical level all the way to the system level (cross-layer approaches). The book aims at demonstrating how new hardware/software co-design solution can be proposed to ef-fectively mitigate reliability degradation such as transistor aging, processor variation, temperature effects, soft errors, etc. Provides readers with latest insights into novel, cross-layer methods and models with respect to dependability of embedded systems; Describes cross-layer approaches that can leverage reliability through techniques that are pro-actively designed with respect to techniques at other layers; Explains run-time adaptation and concepts/means of self-organization, in order to achieve error resiliency in complex, future many core systems.
Resource management has a long history in computing, from the early days of time-shared machines with pioneering fundamental work on run-time systems, distributed systems, real-time operating systems and middleware. The longevity and fundamental importance of the topic has resulted in an incredibly large body of work for on-chip resource management in the past two decades. The possible combinations of sub-topics and variations in the assumptions, use of different terminology, metrics, goals, and use-cases, leaves anyone attempting to review the literature overwhelmed. On-Chip Dynamic Resource Management is the first comprehensive and coherent review of all aspects of on-chip run-time resource management designed to facilitate understanding of recent trends in dynamic and adaptive strategies. The authors provide the reader with a framework within which they can navigate both existing, as well as evolving research efforts in on-chip dynamic resource management. Written by leading experts in the field, researchers and students are provided a structured review and discussion of the state of the art that is divided along the primary objectives of resource management techniques: performance, power, reliability and quality of service.
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